This application is based on Patent Application Ser. No. 2001-319525, filed in Japan, the contents of which are hereby incorporated by reference.
(1) Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and in particular to a technology for rewriting content that has been recorded in such semiconductor memory device.
(2) Description of Related Art
In recent years, with the development of the information communication technology, various types of computers including personal computers have been widespread. Such computers normally use DRAM (dynamic random access memory), SRAM (static RAM), as their main memory device. Since DRAM and SRAM are volatile memories, they need to receive power all the time, in order to retain the data having been stored therein. If a power supply is stopped due to an accident and others, the stored data will be lost.
To cope with the stated problem, an information processing apparatus has been proposed, for example, as disclosed by a Japanese Laid-open Patent Application No. H06-259172. The information processing apparatus disclosed by this prior art has a structure shown in FIG. 1. In the information processing apparatus, when the battery control apparatus detects a reduction in battery voltage, the CPU (central processing unit) instructs to save the data from RAM into the external memory device, while the information processing apparatus is receiving power from the sub-battery.
By the above stated structure, upon detection of a voltage reduction in the main power source, the main power source is replaced with a backup power source, and at the same time the data initially stored in the volatile memory will be saved into a non-volatile memory. This will prevent the loss of the stored data, which would result from a malfunction of the main power source.
However, in the information processing apparatus, data will be first read from the volatile memory according to the CPU instruction, and then saved in the non-volatile memory. Therefore, until the completion of such data saving, power should be kept supplied to all the circuit-constituting devices including the CPU that are included in the information processing apparatus. This is problematic because it requires a large backup power source.
Nevertheless, a non-volatile memory has a limitation on the number of erase/write cycles (i.e. about 1010 cycles for ferroelectric RAM, and about 105 cycles for flash memory), therefore cannot be adopted as a main memory device.
The object of the present invention, in view of the stated problems, is to provide a semiconductor memory device that retains data without requiring a large-scale backup power source if there is a power loss, and that has enhanced erase/write cycle endurance.
In order to achieve this object, the semiconductor memory device according to the present invention is characterized by being included in one chip, and having: a volatile memory; a non-volatile memory; a volatile memory access unit operable to allow a device external to the chip to access the volatile memory; a data save unit operable to save data from the volatile memory to the non-volatile memory; and a power-supply unit operable to accumulate power therein, and supply the accumulated power to the data save unit for use in saving data, where the volatile memory, the non-volatile memory, the volatile memory access unit, the data save unit, and the power-supply unit are integrated into the chip.
In the above construction, the volatile memory will be accessed when there is a request external to the chip for writing data. Accordingly, there will be no increase in number of erase/write cycles performed for the non-volatile memory, at a time when a device external to the chip has written data.
In addition, a sufficient amount of power to be supplied by the power-supply unit, when it is functioning as a backup power source, is an amount required by the semiconductor memory device for saving data. Therefore, unlike the conventional technology, the present invention does not require operation of the whole circuit including the semiconductor memory for saving data, and so a large backup power source is not necessary.
Here, the semiconductor memory device may further include a condition-change detect unit operable to detect a change of a condition of a power supply to the chip from a source external to the chip, where the data save unit saves the data from the volatile memory to the non-volatile memory when the condition-change detect unit detects a change from power-on to power-off.
Here, the semiconductor memory device may further include a data restore unit operable to restore data having been stored in the non-volatile memory into the volatile memory when the condition-change detect unit detects a change from power-off to power-on. This construction enables users to use the semiconductor memory device of the present invention as a volatile memory.
Here, the semiconductor memory device may further include an area-designation receive unit operable to receive a designation of a memory area in the non-volatile memory, where the data save unit saves the data to the designated memory area.
Here, the semiconductor memory device may further include a non-volatile memory access unit operable to allow a device external to the chip to read data from the non-volatile memory. With this construction, the capacity of the semiconductor memory device as a non-volatile memory device is enlarged, without increasing the volatile memory in capacity. Accordingly, it becomes possible to reduce the cost of the semiconductor memory device, and further to reduce the size thereof.
Here, the non-volatile memory may be one of a flash memory and a ferroelectric RAM. With this construction, the amount of power required in saving data from the volatile memory to the non-volatile memory will be reduced. Accordingly, the power to be accumulated within the semiconductor memory device will be reduced. This will lead to a reduction in size of the semiconductor memory device.
Here, the power-supply unit may be one of a chargeable secondary battery, a capacitor, and a reactance element, and accumulates power supplied to the chip from a source external to the chip. Use of such devices enables accumulation of necessary power while the power is supplied to the chip from a source external to the chip, and enables use of the accumulated power when a source external to the chip has stopped supplying power to the chip.